Configuration for a PADI bus block.
Common STP configuration shared by synapse drivers per vertical half.
A container for the PADI event trigger register.
#define GENPYBIND_TAG_HALDLS_VX_V2
haldls::vx::CommonPADIBusConfig CommonPADIBusConfig
haldls::vx::PADIEvent PADIEvent
haldls::vx::CommonSTPConfig CommonSTPConfig