2 #include "hate/visibility.h"
20 haldls::vx::InstructionTimeoutConfig instruction_timeout;
23 haldls::vx::ShiftRegister shift_register;
26 lola::vx::DACControlBlock dac_control_block;
29 lola::vx::DACChannelBlock dac_channel_block;
39 haldls::vx::JTAGClockScaler jtag_clock_scaler;
42 haldls::vx::v2::PLLClockOutputBlock pll_clock_output_block;
45 typedef halco::common::typed_array<haldls::vx::ADPLL, halco::hicann_dls::vx::v2::ADPLLOnDLS>
55 haldls::vx::CommonPhyConfigFPGA common_phy_config_fpga;
58 haldls::vx::CommonPhyConfigChip common_phy_config_chip;
61 typedef halco::common::
62 typed_array<haldls::vx::PhyConfigFPGA, halco::hicann_dls::vx::v2::PhyConfigFPGAOnDLS>
67 typedef halco::common::
68 typed_array<haldls::vx::PhyConfigChip, halco::hicann_dls::vx::v2::PhyConfigChipOnDLS>
73 haldls::vx::SystimeSyncBase systime_sync_base;
89 bool enable_highspeed_link;
92 lola::vx::v2::MemoryTiming memory_timing;
95 haldls::vx::SynapseBiasSelection synapse_bias_selection;
104 haldls::vx::v2::ReferenceGeneratorConfig reference_generator_config;
107 typedef halco::common::typed_array<
108 haldls::vx::v2::CapMemBlockConfig,
109 halco::hicann_dls::vx::v2::CapMemBlockConfigOnDLS>
115 typedef halco::common::
116 typed_array<haldls::vx::v2::CapMemBlock, halco::hicann_dls::vx::v2::CapMemBlockOnDLS>
122 GENPYBIND(stringstream)
123 friend std::ostream& operator<<(std::ostream& os,
InitGenerator const& sequence) SYMBOL_VISIBLE;
170 typedef halco::common::typed_array<
171 haldls::vx::CommonNeuronBackendConfig,
172 halco::hicann_dls::vx::v2::CommonNeuronBackendConfigOnDLS>
177 typedef halco::common::typed_array<
178 haldls::vx::v2::ColumnCorrelationQuad,
179 halco::hicann_dls::vx::v2::ColumnCorrelationQuadOnDLS>
184 typedef halco::common::typed_array<
185 haldls::vx::v2::ColumnCurrentQuad,
186 halco::hicann_dls::vx::v2::ColumnCurrentQuadOnDLS>
191 typedef halco::common::typed_array<
192 haldls::vx::v2::CommonCorrelationConfig,
193 halco::hicann_dls::vx::v2::CommonCorrelationConfigOnDLS>
209 #if defined(__GENPYBIND__) or defined(__GENPYBIND_GENERATED__)
213 : public ExperimentInit
214 , public PlaybackGenerator
216 virtual pybind11::tuple generate() const override
218 return stadls::vx::detail::py_generate_impl(static_cast<ExperimentInit>(*this));
222 // TODO: we can't use the alias above, cf. https://github.com/kljohann/genpybind/issues/32
223 struct GENPYBIND(expose_as(DigitalInit), inline_base("*
DigitalInit*
")) PyDigitalInit
225 , public PlaybackGenerator
227 virtual pybind11::tuple generate() const override
229 return stadls::vx::detail::py_generate_impl(static_cast<DigitalInit>(*this));
233 } // namespace detail
234 #endif // defined(__GENPYBIND__) or defined(__GENPYBIND_GENERATED__)
239 [](::stadls::vx::v2::ExperimentInit const& seq) {
240 return ::stadls::vx::detail::py_generate_impl(seq);
242 pybind11::return_value_policy::move);
248 [](::stadls::vx::v2::DigitalInit const& seq) {
249 return ::stadls::vx::detail::py_generate_impl(seq);
251 pybind11::return_value_policy::move);
254 } // namespace stadls::vx::v2
Sequential PlaybackProgram builder.
Generator for initialization of the chip up to digital communication.
DigitalInit() SYMBOL_VISIBLE
Default constructor.
Generator for initialization required for typical experiments.
halco::common::typed_array< haldls::vx::CommonNeuronBackendConfig, halco::hicann_dls::vx::v2::CommonNeuronBackendConfigOnDLS > common_neuron_backend_config_type
Set common neuron backend with clocks enabled.
halco::common::typed_array< haldls::vx::v2::ColumnCurrentQuad, halco::hicann_dls::vx::v2::ColumnCurrentQuadOnDLS > column_current_quad_type
Set ColumnCurrentQuad/Switch connections.
halco::common::typed_array< haldls::vx::v2::CommonCorrelationConfig, halco::hicann_dls::vx::v2::CommonCorrelationConfigOnDLS > common_correlation_config_type
Set common correlation config.
halco::common::typed_array< haldls::vx::v2::ColumnCorrelationQuad, halco::hicann_dls::vx::v2::ColumnCorrelationQuadOnDLS > column_correlation_quad_type
Set ColumnCorrelationQuad/Switch connections.
ExperimentInit() SYMBOL_VISIBLE
Default constructor.
halco::common::typed_array< haldls::vx::v2::CapMemBlock, halco::hicann_dls::vx::v2::CapMemBlockOnDLS > capmem_block_type
Set initial CapMem config.
halco::common::typed_array< haldls::vx::ADPLL, halco::hicann_dls::vx::v2::ADPLLOnDLS > adplls_type
ADPLL setting.
InitGenerator() SYMBOL_VISIBLE
Default constructor.
halco::common::typed_array< haldls::vx::v2::CapMemBlockConfig, halco::hicann_dls::vx::v2::CapMemBlockConfigOnDLS > capmem_block_config_type
Initialize the CapMem with usable default values.
#define GENPYBIND_TAG_STADLS_VX_V2
auto generate(Ts &&... args) -> decltype(stadls::vx::generate(std::forward< Ts >(args)...))
Return type of generate() call on playback sequence.
HighspeedLink() SYMBOL_VISIBLE
Default constructor.
halco::common::typed_array< haldls::vx::PhyConfigFPGA, halco::hicann_dls::vx::v2::PhyConfigFPGAOnDLS > phy_configs_fpga_type
Highspeed-link PHY settings for the FPGA side.
halco::common::typed_array< haldls::vx::PhyConfigChip, halco::hicann_dls::vx::v2::PhyConfigChipOnDLS > phy_configs_chip_type
Highspeed-link PHY settings for the chip side.