| ►Chalco::common::detail:: RantWrapper | |
| Chaldls::vx::BackgroundSpikeSource::Mask | NeuronLabel bit randomization mask |
| Chaldls::vx::BackgroundSpikeSource::Period | Inter-spike interval for regular and inter-bin interval for Poisson spike generation |
| Chaldls::vx::BackgroundSpikeSource::Rate | Rate of spike output in the Poisson spike generation mode, without effect in regular mode |
| Chaldls::vx::BackgroundSpikeSource::Seed | Random seed for random number generation |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::PauseCounter | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::SubCounter | |
| Chaldls::vx::CommonCorrelationConfig::ResetDuration | Duration of correlation reset for synapses (+3 ppu clock cycles) |
| Chaldls::vx::CommonCorrelationConfig::ResetFallTime | Wait time in PPU clock cycles after disabling the correlation column reset enable |
| Chaldls::vx::CommonCorrelationConfig::SenseDelay | Wait time in PPU clock cycles between connecting the outputs of a synapse to the CADC inputs and starting the CADC read |
| Chaldls::vx::CrossbarInputDropCounter::Value | |
| Chaldls::vx::CrossbarOutputEventCounter::Value | |
| Chaldls::vx::DACChannel::Value | |
| Chaldls::vx::PLLSelfTest::CheckValue | Expected counter value within the 2^(p + 2) reference cycles |
| Chaldls::vx::PLLSelfTestStatus::CounterValue | Measured counter value in previous self-test execution |
| Chaldls::vx::detail::SRAMTimingConfig::AddressSetupTime | Wait time for address value propagation after enable signal pull |
| Chaldls::vx::detail::SRAMTimingConfig::EnableWidth | Duration of enable signal pull |
| Chaldls::vx::detail::SRAMTimingConfig::ReadDelay | Wait time after enable signal pull for cells to drive their value until read |
| Chaldls::vx::AD5252ChannelConfig | |
| Chaldls::vx::AD5252ChannelConfigPersistent | |
| Chaldls::vx::AddPickle< TL > | Add pickle support to list of classes |
| Chaldls::vx::AddPickle< hate::type_list< Ts... > > | |
| Chaldls::vx::ADPLL | Container for configuration of an ADPLL (All-Digital Phased-Locked-Loop) clock generator |
| Chaldls::vx::detail::backend_container_type_from_backend< B > | |
| Chaldls::vx::detail::backend_from_backend_container_type< BackendContainer > | |
| Chaldls::vx::detail::BackendContainerBase< ContainerT, DefaultBackendContainer, AdditionalBackendContainer > | Backend container trait base |
| ►Chaldls::vx::detail::BackendContainerBase< AD5252ChannelConfig, fisch::vx::word_access_type::I2CAD5252RwRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< AD5252ChannelConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< AD5252ChannelConfigPersistent, fisch::vx::word_access_type::I2CAD5252RwRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< AD5252ChannelConfigPersistent > | |
| ►Chaldls::vx::detail::BackendContainerBase< ADPLL, fisch::vx::word_access_type::JTAGPLLRegister, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< ADPLL > | The JTAGPLLRegister backend only provides write functionality, but is safe with respect to changing the ADPLL config |
| ►Chaldls::vx::detail::BackendContainerBase< BackgroundSpikeSource, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< BackgroundSpikeSource > | |
| ►Chaldls::vx::detail::BackendContainerBase< BlockPostPulse, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< BlockPostPulse > | |
| ►Chaldls::vx::detail::BackendContainerBase< CADCChannelConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CADCChannelConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< CADCConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CADCConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< CADCOffsetSRAMTimingConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CADCOffsetSRAMTimingConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< CADCSampleQuad, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< CADCSampleQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< CapMemBlock< Coordinates >, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CapMemBlock< Coordinates > > | |
| ►Chaldls::vx::detail::BackendContainerBase< CapMemBlockConfig< Coordinates >, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CapMemBlockConfig< Coordinates > > | |
| ►Chaldls::vx::detail::BackendContainerBase< CapMemCell< Coordinates >, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CapMemCell< Coordinates > > | |
| ►Chaldls::vx::detail::BackendContainerBase< ColumnCorrelationQuad, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< ColumnCorrelationQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< ColumnCurrentQuad, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< ColumnCurrentQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< CommonNeuronBackendConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CommonNeuronBackendConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< CommonPADIBusConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CommonPADIBusConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< CommonPhyConfigChip, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CommonPhyConfigChip > | |
| ►Chaldls::vx::detail::BackendContainerBase< CommonPhyConfigFPGA, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< CommonPhyConfigFPGA > | |
| ►Chaldls::vx::detail::BackendContainerBase< CommonSTPConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CommonSTPConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< CommonSynramConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CommonSynramConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< ContainerT, ContainerT > | |
| Chaldls::vx::detail::BackendContainerTrait< ContainerT > | |
| ►Chaldls::vx::detail::BackendContainerBase< CorrelationReset, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CorrelationReset > | |
| ►Chaldls::vx::detail::BackendContainerBase< CrossbarInputDropCounter, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CrossbarInputDropCounter > | |
| ►Chaldls::vx::detail::BackendContainerBase< CrossbarNode, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CrossbarNode > | |
| ►Chaldls::vx::detail::BackendContainerBase< CrossbarOutputConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CrossbarOutputConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< CrossbarOutputEventCounter, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CrossbarOutputEventCounter > | |
| ►Chaldls::vx::detail::BackendContainerBase< CurrentDAC, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CurrentDAC > | |
| ►Chaldls::vx::detail::BackendContainerBase< DAC6573ChannelConfig, fisch::vx::word_access_type::I2CDAC6573RwRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< DAC6573ChannelConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< DACChannel, fisch::vx::word_access_type::SPIDACDataRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< DACChannel > | |
| ►Chaldls::vx::detail::BackendContainerBase< DACControl, fisch::vx::word_access_type::SPIDACControlRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< DACControl > | |
| ►Chaldls::vx::detail::BackendContainerBase< EventRecordingConfig, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< EventRecordingConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< ExternalPPUMemoryByte, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< ExternalPPUMemoryByte > | |
| ►Chaldls::vx::detail::BackendContainerBase< ExternalPPUMemoryQuad, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< ExternalPPUMemoryQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< FPGADeviceDNA, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< FPGADeviceDNA > | |
| ►Chaldls::vx::detail::BackendContainerBase< haldls::vx::CommonCorrelationConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< CommonCorrelationConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< HicannARQStatus, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< HicannARQStatus > | |
| ►Chaldls::vx::detail::BackendContainerBase< INA219Config, fisch::vx::word_access_type::I2CINA219RwRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< INA219Config > | |
| ►Chaldls::vx::detail::BackendContainerBase< INA219Status, fisch::vx::word_access_type::I2CINA219RoRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< INA219Status > | |
| ►Chaldls::vx::detail::BackendContainerBase< InstructionTimeoutConfig, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< InstructionTimeoutConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< JTAGClockScaler, fisch::vx::word_access_type::JTAGClockScaler > | |
| Chaldls::vx::detail::BackendContainerTrait< JTAGClockScaler > | |
| ►Chaldls::vx::detail::BackendContainerBase< JTAGIdCode, fisch::vx::word_access_type::JTAGIdCode > | |
| Chaldls::vx::detail::BackendContainerTrait< JTAGIdCode > | |
| ►Chaldls::vx::detail::BackendContainerBase< MADCConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< MADCConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< MADCControl, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< MADCControl > | |
| ►Chaldls::vx::detail::BackendContainerBase< NeuronBackendConfig< Coordinates >, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< NeuronBackendConfig< Coordinates > > | |
| ►Chaldls::vx::detail::BackendContainerBase< NeuronBackendSRAMTimingConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< NeuronBackendSRAMTimingConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< NeuronReset, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< NeuronReset > | |
| ►Chaldls::vx::detail::BackendContainerBase< NeuronSRAMTimingConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< NeuronSRAMTimingConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< NullPayloadReadable, fisch::vx::word_access_type::NullPayloadReadable > | |
| Chaldls::vx::detail::BackendContainerTrait< NullPayloadReadable > | |
| ►Chaldls::vx::detail::BackendContainerBase< PADIEvent, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PADIEvent > | |
| ►Chaldls::vx::detail::BackendContainerBase< PadMultiplexerConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PadMultiplexerConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< PerfTest, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< PerfTest > | |
| ►Chaldls::vx::detail::BackendContainerBase< PerfTestStatus, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< PerfTestStatus > | |
| ►Chaldls::vx::detail::BackendContainerBase< PhyConfigChip, fisch::vx::word_access_type::JTAGPhyRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< PhyConfigChip > | |
| ►Chaldls::vx::detail::BackendContainerBase< PhyConfigFPGA, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< PhyConfigFPGA > | |
| ►Chaldls::vx::detail::BackendContainerBase< PhyStatus, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< PhyStatus > | |
| ►Chaldls::vx::detail::BackendContainerBase< PLLSelfTest, fisch::vx::word_access_type::JTAGPLLRegister, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PLLSelfTest > | |
| ►Chaldls::vx::detail::BackendContainerBase< PLLSelfTestStatus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PLLSelfTestStatus > | |
| ►Chaldls::vx::detail::BackendContainerBase< PollingOmnibusBlock, fisch::vx::word_access_type::PollingOmnibusBlock > | |
| Chaldls::vx::detail::BackendContainerTrait< PollingOmnibusBlock > | |
| ►Chaldls::vx::detail::BackendContainerBase< PollingOmnibusBlockConfig, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< PollingOmnibusBlockConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< PPUControlRegister, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PPUControlRegister > | |
| ►Chaldls::vx::detail::BackendContainerBase< PPUMemory, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PPUMemory > | |
| ►Chaldls::vx::detail::BackendContainerBase< PPUMemoryBlock, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PPUMemoryBlock > | |
| ►Chaldls::vx::detail::BackendContainerBase< PPUMemoryWord, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PPUMemoryWord > | |
| ►Chaldls::vx::detail::BackendContainerBase< PPUStatusRegister, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< PPUStatusRegister > | |
| ►Chaldls::vx::detail::BackendContainerBase< ReadoutSourceSelection, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< ReadoutSourceSelection > | |
| ►Chaldls::vx::detail::BackendContainerBase< ResetChip, fisch::vx::word_access_type::ResetChip > | |
| Chaldls::vx::detail::BackendContainerTrait< ResetChip > | |
| ►Chaldls::vx::detail::BackendContainerBase< ResetJTAGTap, fisch::vx::word_access_type::ResetJTAGTap > | |
| Chaldls::vx::detail::BackendContainerTrait< ResetJTAGTap > | |
| ►Chaldls::vx::detail::BackendContainerBase< ShiftRegister, fisch::vx::word_access_type::SPIShiftRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< ShiftRegister > | |
| ►Chaldls::vx::detail::BackendContainerBase< SpikeCounterRead, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SpikeCounterRead > | |
| ►Chaldls::vx::detail::BackendContainerBase< SpikeCounterReset, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SpikeCounterReset > | |
| ►Chaldls::vx::detail::BackendContainerBase< SpikePack1ToChip, fisch::vx::word_access_type::SpikePack1ToChip > | |
| Chaldls::vx::detail::BackendContainerTrait< SpikePack1ToChip > | |
| ►Chaldls::vx::detail::BackendContainerBase< SpikePack2ToChip, fisch::vx::word_access_type::SpikePack2ToChip > | |
| Chaldls::vx::detail::BackendContainerTrait< SpikePack2ToChip > | |
| ►Chaldls::vx::detail::BackendContainerBase< SpikePack3ToChip, fisch::vx::word_access_type::SpikePack3ToChip > | |
| Chaldls::vx::detail::BackendContainerTrait< SpikePack3ToChip > | |
| ►Chaldls::vx::detail::BackendContainerBase< SynapseBiasSelection, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SynapseBiasSelection > | |
| ►Chaldls::vx::detail::BackendContainerBase< SynapseCorrelationCalibQuad, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SynapseCorrelationCalibQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< SynapseDriverConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SynapseDriverConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< SynapseDriverSRAMTimingConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SynapseDriverSRAMTimingConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< SynapseLabelQuad, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SynapseLabelQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< SynapseQuad, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SynapseQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< SynapseWeightQuad, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SynapseWeightQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< SystimeSync, fisch::vx::word_access_type::SystimeSync > | |
| Chaldls::vx::detail::BackendContainerTrait< SystimeSync > | |
| ►Chaldls::vx::detail::BackendContainerBase< SystimeSyncBase, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< SystimeSyncBase > | |
| ►Chaldls::vx::detail::BackendContainerBase< TCA9554Config, fisch::vx::word_access_type::I2CTCA9554RwRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< TCA9554Config > | |
| ►Chaldls::vx::detail::BackendContainerBase< TCA9554Inputs, fisch::vx::word_access_type::I2CTCA9554RoRegister > | |
| Chaldls::vx::detail::BackendContainerTrait< TCA9554Inputs > | |
| ►Chaldls::vx::detail::BackendContainerBase< Timer, fisch::vx::word_access_type::Timer > | |
| Chaldls::vx::detail::BackendContainerTrait< Timer > | |
| ►Chaldls::vx::detail::BackendContainerBase< v2::NeuronConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< v2::NeuronConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< v2::NeuronResetQuad, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< v2::NeuronResetQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< v2::PLLClockOutputBlock, fisch::vx::word_access_type::JTAGPLLRegister, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< v2::PLLClockOutputBlock > | |
| ►Chaldls::vx::detail::BackendContainerBase< v2::ReferenceGeneratorConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< v2::ReferenceGeneratorConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< v3::NeuronConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< v3::NeuronConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< v3::NeuronResetQuad, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< v3::NeuronResetQuad > | |
| ►Chaldls::vx::detail::BackendContainerBase< v3::PLLClockOutputBlock, fisch::vx::word_access_type::JTAGPLLRegister, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< v3::PLLClockOutputBlock > | |
| ►Chaldls::vx::detail::BackendContainerBase< v3::ReferenceGeneratorConfig, fisch::vx::word_access_type::Omnibus, fisch::vx::word_access_type::OmnibusChipOverJTAG > | |
| Chaldls::vx::detail::BackendContainerTrait< v3::ReferenceGeneratorConfig > | |
| ►Chaldls::vx::detail::BackendContainerBase< VectorGeneratorControl, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< VectorGeneratorControl > | |
| ►Chaldls::vx::detail::BackendContainerBase< VectorGeneratorFIFOWord, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< VectorGeneratorFIFOWord > | |
| ►Chaldls::vx::detail::BackendContainerBase< VectorGeneratorLUTEntry, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< VectorGeneratorLUTEntry > | |
| ►Chaldls::vx::detail::BackendContainerBase< VectorGeneratorNotificationAddress, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< VectorGeneratorNotificationAddress > | |
| ►Chaldls::vx::detail::BackendContainerBase< VectorGeneratorTrigger, fisch::vx::word_access_type::Omnibus > | |
| Chaldls::vx::detail::BackendContainerTrait< VectorGeneratorTrigger > | |
| Chaldls::vx::BackgroundSpikeSource | Background spike source on chip |
| Chaldls::vx::Barrier | |
| ►Chalco::common::detail::BaseType | |
| Chaldls::vx::CurrentDAC::Current | Value of current DAC |
| Chaldls::vx::ExternalPPUMemoryByte::Value | |
| Chaldls::vx::HicannARQStatus::ReadCount | Number of words submitted to the ARQ from the Chip |
| Chaldls::vx::HicannARQStatus::RxCount | Number of words sent from the ARQ from the Chip to the FPGA |
| Chaldls::vx::HicannARQStatus::TxCount | Number of words sent from the ARQ from the FPGA to the Chip |
| Chaldls::vx::HicannARQStatus::WriteCount | Number of words submitted to the ARQ from the FPGA |
| Chaldls::vx::PhyStatus::CRCErrorCount | Number of CRC errors since last reset |
| Chaldls::vx::PhyStatus::OnlineTime | Online time in cycles since last reset |
| Chaldls::vx::PhyStatus::RxCount | Number of rx words from Chip since last reset |
| Chaldls::vx::PhyStatus::RxDroppedCount | Number of dropped rx words |
| Chaldls::vx::PhyStatus::TxCount | Number of tx words to Chip since last reset |
| Chaldls::vx::SpikeLabel | |
| Chaldls::vx::Timer::Value | |
| Chaldls::vx::BlockPostPulse | Container to send post pulses to one half of the neurons (left/right) |
| Chaldls::vx::CADCChannelConfig | CADC container with channel-local digital offset config |
| Chaldls::vx::CADCConfig | CADC container with global digital config for a vertical half |
| Chaldls::vx::CADCSampleQuad | CADC container of four CADC samples |
| Chaldls::vx::v2::PLLClockOutputBlock::ClockOutput | |
| Chaldls::vx::v3::PLLClockOutputBlock::ClockOutput | |
| Chaldls::vx::ColumnCorrelationQuad::ColumnCorrelationSwitch | |
| Chaldls::vx::ColumnCurrentQuad::ColumnCurrentSwitch | |
| Chaldls::vx::CommonCorrelationConfig | Correlation reset and readout timing configuration container |
| Chaldls::vx::CommonPhyConfigChip | Container for configuration of enable values for the chip-side PHYs |
| Chaldls::vx::CommonPhyConfigFPGA | Container for configuration of enable values for the FPGA-side PHYs |
| Chaldls::vx::CorrelationReset | Container to trigger reset of correlation measurements on a synapse quad |
| Chaldls::vx::CrossbarInputDropCounter | Crossbar input drop counter accumulating drops at all outputs for which the drop counter accumulation is enabled in the corresponding CrossbarNode |
| Chaldls::vx::CrossbarNode | Node of the crossbar routing events from a CrossbarInputOnDLS to a CrossbarOutputOnDLS |
| Chaldls::vx::CrossbarOutputConfig | |
| Chaldls::vx::CrossbarOutputEventCounter | Crossbar output event counter counting events routed to an output |
| Chaldls::vx::CurrentDAC | Configuration of the current DAC of the readout chain |
| Chaldls::vx::DAC6573ChannelConfig | |
| ►Chaldls::vx::DifferentialWriteTrait | Trait signalling derived-from container type support differential write operation |
| Chaldls::vx::CapMemBlock< Coordinates > | |
| Chaldls::vx::CapMemBlockConfig< Coordinates > | |
| Chaldls::vx::CapMemCell< Coordinates > | |
| Chaldls::vx::ColumnCorrelationQuad | |
| Chaldls::vx::ColumnCurrentQuad | |
| Chaldls::vx::CommonNeuronBackendConfig | Read/write access to common neuron parameters |
| Chaldls::vx::CommonPADIBusConfig | Configuration for a PADI bus block |
| Chaldls::vx::CommonSTPConfig | Common STP configuration shared by synapse drivers per vertical half |
| Chaldls::vx::CommonSynramConfig | |
| Chaldls::vx::DACChannel | Container for individual configuration of the value of a DAC channel of the xBoard DACs |
| Chaldls::vx::DACControl | Container for enabling DAC channels of a xBoard DAC |
| Chaldls::vx::NeuronBackendConfig< Coordinates > | Read/write access to the NeuronBackend container |
| Chaldls::vx::PPUControlRegister | |
| Chaldls::vx::ShiftRegister | Container for configuration of the 24-bit wide shift register controlling six VDD switches, the selection of the ADC source, ADC power down and reset pins, six LEDs, routing two DAC channels to a differential debug line and the CapMem reference current connection |
| Chaldls::vx::SynapseCorrelationCalibQuad | |
| Chaldls::vx::SynapseDriverConfig | |
| Chaldls::vx::SynapseLabelQuad | |
| Chaldls::vx::SynapseQuad | |
| Chaldls::vx::SynapseWeightQuad | |
| Chaldls::vx::v2::NeuronConfig | |
| Chaldls::vx::v3::NeuronConfig | |
| Chaldls::vx::EventRecordingConfig | Container for the event (spikes, MADC samples) recording configuration register |
| Chaldls::vx::ExternalPPUMemoryByte | |
| Chaldls::vx::ExternalPPUMemoryQuad | |
| ►Cstd::false_type | |
| Chaldls::vx::HasLocalData< T, typename > | |
| Chaldls::vx::detail::IsReadable< T, typename > | |
| Chaldls::vx::detail::IsWriteable< T, typename > | |
| Chaldls::vx::FPGADeviceDNA | Container for reading out the unique identifier of the FPGA |
| Chaldls::vx::detail::gen_is_read_and_writeable_lookup_table< TL > | Generate lookup table from backend to readable and writable property |
| Chaldls::vx::detail::gen_is_read_and_writeable_lookup_table< hate::type_list< Ts... > > | |
| Chaldls::vx::detail::BackendContainerBase< ContainerT, DefaultBackendContainer, AdditionalBackendContainer >::generate_lookup_table< TL > | |
| Chaldls::vx::detail::BackendContainerBase< ContainerT, DefaultBackendContainer, AdditionalBackendContainer >::generate_lookup_table< hate::type_list< Ts... > > | |
| ►CT::has_local_data | |
| Chaldls::vx::HasLocalData< T, typename boost::enable_if_has_type< typename T::has_local_data >::type > | |
| Chaldls::vx::HicannARQStatus | |
| Chaldls::vx::HighspeedLinkNotification | Highspeed-Link notification from chip |
| Chaldls::vx::INA219Config | |
| Chaldls::vx::INA219Status | |
| Chaldls::vx::InstructionTimeoutConfig | Container for the configuration of the playback instruction timeout duration |
| ►CT::is_leaf_node | |
| Chaldls::vx::HasLocalData< T, typename boost::enable_if_has_type< typename T::is_leaf_node >::type > | |
| Chaldls::vx::detail::IsReadable< T, typename boost::enable_if_has_type< decltype(T::read_config_size_in_words)>::type > | |
| Chaldls::vx::detail::IsWriteable< T, typename boost::enable_if_has_type< decltype(T::write_config_size_in_words)>::type > | |
| Chaldls::vx::detail::IsWriteReadable< T > | |
| Chaldls::vx::JTAGClockScaler | Container writing JTAG clock-scaler value |
| Chaldls::vx::JTAGIdCode | Container for reading the JTAG IDCODE |
| Chaldls::vx::MADCConfig | Configuration container for MADC and related circuitry |
| Chaldls::vx::MADCControl | Container for MADC control state machine |
| Chaldls::vx::MADCSampleFromChip | MADCSample from chip |
| Chaldls::vx::detail::MADCSampleFromChipChecker | |
| Chaldls::vx::NeuronReset | Container to trigger reset of a single neuron |
| Chaldls::vx::v2::NeuronResetQuad | Container to trigger reset of a quad of neurons at once |
| Chaldls::vx::v3::NeuronResetQuad | Container to trigger reset of a quad of neurons at once |
| Chaldls::vx::NullPayloadReadable | |
| Chaldls::vx::PADIEvent | A container for the PADI event trigger register |
| Chaldls::vx::PadMultiplexerConfig | A configuration container for the top-level readout mux, selecting the connections between an analog readout pad and different components on the chip |
| Chaldls::vx::PerfTest | Container for enabling highspeed perf test |
| Chaldls::vx::PerfTestStatus | Container for perf test result readout |
| ►Chaldls::vx::detail::PhyConfigBase | Common base class for PhyConfig of the FPGA- and chip-side PHYs |
| Chaldls::vx::PhyConfigChip | Container for individual configuration of chip-side PHYs |
| Chaldls::vx::PhyConfigFPGA | Container for individual configuration of FPGA-side PHYs |
| Chaldls::vx::PhyStatus | |
| Chaldls::vx::v2::PLLClockOutputBlock | Container for configuration of the clock outputs of the PLL |
| Chaldls::vx::v3::PLLClockOutputBlock | Container for configuration of the clock outputs of the PLL |
| Chaldls::vx::PLLSelfTest | Container for configuration and triggering of the PLL internal self test |
| Chaldls::vx::PLLSelfTestStatus | Container of PLL self-test status data |
| Chaldls::vx::PollingOmnibusBlock | Container for polling block operation on a Omnibus address |
| Chaldls::vx::PollingOmnibusBlockConfig | |
| Chaldls::vx::PPUMemory | |
| Chaldls::vx::PPUMemoryBlock | |
| Chaldls::vx::PPUMemoryWord | |
| Chaldls::vx::PPUStatusRegister | |
| ►Chalco::common::detail::RantWrapper | |
| CReferenceGeneratorConfig::CapMemAmplifier | |
| CReferenceGeneratorConfig::CapMemAmplifier | |
| CReferenceGeneratorConfig::CapMemOffset | |
| CReferenceGeneratorConfig::CapMemOffset | |
| CReferenceGeneratorConfig::CapMemSlope | |
| CReferenceGeneratorConfig::CapMemSlope | |
| CReferenceGeneratorConfig::ReferenceControl | |
| CReferenceGeneratorConfig::ReferenceControl | |
| CReferenceGeneratorConfig::ResistorControl | |
| CReferenceGeneratorConfig::ResistorControl | |
| Chaldls::vx::AD5252ChannelConfig::WiperSetting | |
| Chaldls::vx::AD5252ChannelConfigPersistent::WiperSetting | |
| Chaldls::vx::ADPLL::CoreDivM0 | Divider to set the output frequency f_clk_core0 (Together with PreDivP1) |
| Chaldls::vx::ADPLL::CoreDivM1 | Divider to set the output frequency f_clk_core1 (Together with PreDivP1) |
| Chaldls::vx::ADPLL::DcoPowerSwitch | Number of activated PMOS header power switches during DCO operation |
| Chaldls::vx::ADPLL::FilterShift | Loop filter gain boost by 2^n during lock-in, leads to lock time reduction |
| Chaldls::vx::ADPLL::LoopDivN | Divider to set the frequency of the DCO f_dco (Together with PreDivP0) |
| Chaldls::vx::ADPLL::LoopFilterInt | Integral part of the PID controller for the DCO |
| Chaldls::vx::ADPLL::LoopFilterProp | Proportional part of the PID controller for the DCO |
| Chaldls::vx::ADPLL::PreDivP0 | Divider to set the frequency of the DCO f_dco (Together with LoopDivN) |
| Chaldls::vx::ADPLL::PreDivP1 | Divider for f_clk_core0 and f_clk_core1 |
| Chaldls::vx::ADPLL::PreDivP2 | Divider to set the output frequency f_clk_dco |
| Chaldls::vx::ADPLL::Tune | Tune value of the DCO |
| Chaldls::vx::CADCChannelConfig::Offset | Offset value to add to measurement |
| Chaldls::vx::CADCConfig::DeadTime | Dead time in cycles after linear ramp increase to wait for signal propagation to every channel to prevent cutting off leaf channel ramps too early |
| Chaldls::vx::CADCConfig::ResetWait | Wait time in cycles after ramp drop to compensate for analog low-pass filtering of ramp signal and preventing the drop of the last ramp to cause interference in the next linear ramp increase |
| Chaldls::vx::CADCSampleQuad::Value | CADC measurement value (offset-corrected, see CADCChannelConfig) |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::BoostA | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::BoostB | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::BoostFactor | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::CurrentCellRes | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::LevelShifterBias | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::OutAmpBias | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::PrescalePause | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::PrescaleRamp | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::PulseA | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::PulseB | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::SourceFollowerBias | |
| Chaldls::vx::CapMemBlockConfig< Coordinates >::VGlobalBias | |
| Chaldls::vx::CapMemCell< Coordinates >::DisableRefresh | |
| Chaldls::vx::CapMemCell< Coordinates >::Value | |
| Chaldls::vx::CommonNeuronBackendConfig::ClockScale | The ClockScale determines the range of the clock and at its precision It's an exponential power-of-two clock scaling factor: For a given reference clock of f_clk = 250MHz, the resulting frequency is f_clk / (2 ^ (clock_scale + 1)) |
| Chaldls::vx::CommonNeuronBackendConfig::WaitFireNeuron | Duration of pulse triggering the artificial neuron spikes |
| Chaldls::vx::CommonNeuronBackendConfig::WaitGlobalPostPulse | Duration of the pulse triggering global post pulses for all neurons connected to that backend block |
| Chaldls::vx::CommonNeuronBackendConfig::WaitSpikeCounterRead | Wait time for letting the neuron backend circuits drive the counter content to the controller logic |
| Chaldls::vx::CommonNeuronBackendConfig::WaitSpikeCounterReset | Duration of the pulse triggering spike counter resets |
| Chaldls::vx::CommonPADIBusConfig::DacenPulseExtension | |
| Chaldls::vx::CommonSTPConfig::RecoveryClockSpeed | |
| Chaldls::vx::CommonSynramConfig::PCConf | Precharge configuration |
| Chaldls::vx::CommonSynramConfig::WConf | Wordline activation delay |
| Chaldls::vx::CommonSynramConfig::WaitCtrClear | |
| Chaldls::vx::DAC6573ChannelConfig::Value | |
| Chaldls::vx::INA219Status::BusVoltage | Bus voltage with linear conversion and LSB = 4mV |
| Chaldls::vx::INA219Status::ShuntVoltage | Shunt voltage with linear conversion and LSB = 10uV |
| Chaldls::vx::JTAGClockScaler::Value | Clock-scaler value type |
| Chaldls::vx::JTAGIdCode::ManufacturerId | JEDEC Manufacturer ID code, Heidelberg University has '0x057' |
| Chaldls::vx::JTAGIdCode::PartNumber | Device identification number |
| Chaldls::vx::JTAGIdCode::Version | Hardware revision number, starting from 0 |
| Chaldls::vx::MADCConfig::ActiveMuxInputSelectLength | |
| Chaldls::vx::MADCConfig::CalibrationWaitValue | |
| Chaldls::vx::MADCConfig::ConversionCyclesOffset | |
| Chaldls::vx::MADCConfig::MADCClockScaleValue | |
| Chaldls::vx::MADCConfig::NumberOfSamples | |
| Chaldls::vx::MADCConfig::PowerupWaitValue | |
| Chaldls::vx::MADCConfig::PreampGainCapacitorSize | |
| Chaldls::vx::MADCConfig::SARResetLength | |
| Chaldls::vx::MADCConfig::SARResetWait | |
| Chaldls::vx::MADCConfig::SampleDurationAdjust | |
| Chaldls::vx::MADCConfig::SamplingWindowTiming | |
| Chaldls::vx::MADCSampleFromChip::Value | Sample value |
| Chaldls::vx::NeuronBackendAddressOut | Address of the spikes sent out by a neuron |
| Chaldls::vx::NeuronBackendConfig< Coordinates >::InputClock | There are two independent but equivalent clocks available |
| Chaldls::vx::NeuronBackendConfig< Coordinates >::RefractoryTime | The refractory time can be configured to be used for different applications (short and long) Refactory Periods usually range from 0 to 5 ms |
| Chaldls::vx::NeuronBackendConfig< Coordinates >::ResetHoldoff | ResetHoldoff period: Adjusts the time delta between the reset and the refractory period |
| Chaldls::vx::PADIEvent::HagenActivation | Activation payload in Hagen-mode |
| Chaldls::vx::PADIEvent::HagenAddress | Address in Hagen-mode |
| Chaldls::vx::PADIEvent::RowSelectAddress | |
| Chaldls::vx::PLLSelfTest::CheckRange | Acceptance range for the internal counter compared to the expected counter |
| Chaldls::vx::PLLSelfTest::PreScalerP | Selects counting window of the self test |
| Chaldls::vx::PPUMemoryWord::Value | |
| Chaldls::vx::PerfTestStatus::ErrorWord | First non-consecutive payload |
| Chaldls::vx::PerfTestStatus::InOrder | Number of words received in order |
| Chaldls::vx::PerfTestStatus::Received | Number of words received |
| Chaldls::vx::PerfTestStatus::Sent | Number of words sent successfully |
| Chaldls::vx::SpikeCounterRead::Count | Count of rate counter |
| Chaldls::vx::SpikeLabel::PADILabel | Label type processed by PADI-bus, bits 0-10 |
| Chaldls::vx::SynapseCorrelationCalibQuad::AmpCalib | |
| Chaldls::vx::SynapseCorrelationCalibQuad::TimeCalib | |
| Chaldls::vx::SynapseDriverConfig::HagenDACOffset | |
| Chaldls::vx::SynapseDriverConfig::Offset | |
| Chaldls::vx::SynapseDriverConfig::Recovery | |
| Chaldls::vx::SynapseDriverConfig::RowAddressCompareMask | |
| Chaldls::vx::SynapseDriverConfig::TargetVoltages | |
| Chaldls::vx::SynapseDriverConfig::Utilization | |
| Chaldls::vx::SynapseLabelValue | Value type of a single synapse label configuration |
| Chaldls::vx::SynapseWeightQuad::Value | |
| Chaldls::vx::SystimeSyncBase::Value | |
| Chaldls::vx::VectorGeneratorControl::EventPack | Event packing to use |
| Chaldls::vx::VectorGeneratorControl::ResendCount | Number of times to resend same input |
| Chaldls::vx::VectorGeneratorControl::SourceCount | Number of sources to use |
| Chaldls::vx::VectorGeneratorControl::Wait | Wait value to use |
| Chaldls::vx::VectorGeneratorLUTEntry::Value | Entry value describing the bits [5, 15] of the sent spike label |
| Chaldls::vx::detail::PhyConfigBase::DebugOutputs | |
| Chaldls::vx::detail::PhyConfigBase::ManualDelay | |
| Chaldls::vx::detail::PhyConfigBase::VBias | |
| Chaldls::vx::v2::NeuronConfig::MembraneCapacitorSize | Size of membrane capacitor |
| Chaldls::vx::v3::NeuronConfig::MembraneCapacitorSize | Size of membrane capacitor |
| Chaldls::vx::ReadoutSourceSelection | Configuration container for the two mux and buffer blocks for voltage readout |
| CReferenceGeneratorConfig | |
| Chaldls::vx::ResetChip | Container for setting the reset pin of the chip |
| Chaldls::vx::ResetJTAGTap | Container for resetting JTAG state-machine |
| Chaldls::vx::ReadoutSourceSelection::SourceMultiplexer | |
| Chaldls::vx::SpikeCounterRead | Container to read the spike counter of a single neuron |
| Chaldls::vx::SpikeCounterReset | Container to reset the spike counter of a single neuron |
| Chaldls::vx::SpikeFromChip | Spike from chip |
| Chaldls::vx::detail::SpikeFromChipChecker | |
| Chaldls::vx::SpikePack1ToChip | |
| Chaldls::vx::SpikePack2ToChip | |
| Chaldls::vx::SpikePack3ToChip | |
| ►Chaldls::vx::detail::SRAMTimingConfig | Configuration of full-custom SRAM timing |
| Chaldls::vx::CADCOffsetSRAMTimingConfig | |
| Chaldls::vx::NeuronBackendSRAMTimingConfig | |
| Chaldls::vx::NeuronSRAMTimingConfig | |
| Chaldls::vx::SynapseDriverSRAMTimingConfig | |
| Chaldls::vx::SynapseBiasSelection | |
| Chaldls::vx::SystimeSync | Container for syncronization of chip and FPGA systime |
| Chaldls::vx::SystimeSyncBase | Container for configuring the initial counter value of the systime counter in the chip and in the FPGA after the next systime syncronization operation |
| Chaldls::vx::TCA9554Config | |
| Chaldls::vx::TCA9554Inputs | |
| Chaldls::vx::Timer | Container for resetting the FPGA playback timer |
| ►Cstd::true_type | |
| Chaldls::vx::detail::IsReadable< T, std::enable_if_t< hate::is_in_type_list< T, NonLeafNodeReadableContainerList >::value > > | |
| Chaldls::vx::detail::IsReadable< T, typename boost::enable_if_has_type< decltype(T::config_size_in_words)>::type > | |
| Chaldls::vx::detail::IsWriteable< T, std::enable_if_t< hate::is_in_type_list< T, NonLeafNodeWriteableContainerList >::value > > | |
| Chaldls::vx::detail::IsWriteable< T, typename boost::enable_if_has_type< decltype(T::config_size_in_words)>::type > | |
| Chaldls::vx::INA219Status::UncalibratedPower | Uncalibrated power [W] |
| Chaldls::vx::VectorGeneratorControl | |
| Chaldls::vx::VectorGeneratorFIFOWord | Container for writing a word of (maximally) four activation values into the FIFO in front of the vector generator |
| Chaldls::vx::VectorGeneratorLUTEntry | Container for an entry in the lookup-table for generation of spike events from activation values |
| Chaldls::vx::VectorGeneratorNotificationAddress | |
| Chaldls::vx::VectorGeneratorTrigger | |
| Chaldls::vx::detail::VisitPreorderImpl< ContainerT > | Implementation detail of the visit_preorder() free function (q.v.) |
| Chaldls::vx::detail::VisitPreorderImpl< CapMemBlock< Coordinates > > | |
| Chaldls::vx::detail::VisitPreorderImpl< PPUMemory > | |
| Chaldls::vx::detail::VisitPreorderImpl< PPUMemoryBlock > | |
1.9.1