| Ncereal | |
| ▼Nfisch | |
| ►Nvx | |
| Nword_access_type | |
| ▼Nhalco | |
| ►Nhicann_dls | |
| ►Nvx | |
| Nv2 | |
| Nv3 | |
| ▼Nhaldls | |
| ►Nvx | |
| ►Ndetail | |
| Cbackend_container_type_from_backend | |
| Cbackend_from_backend_container_type | |
| ►CBackendContainerBase | Backend container trait base |
| Cgenerate_lookup_table | |
| Cgenerate_lookup_table< hate::type_list< Ts... > > | |
| CBackendContainerTrait | |
| CBackendContainerTrait< AD5252ChannelConfig > | |
| CBackendContainerTrait< AD5252ChannelConfigPersistent > | |
| CBackendContainerTrait< ADPLL > | The JTAGPLLRegister backend only provides write functionality, but is safe with respect to changing the ADPLL config |
| CBackendContainerTrait< BackgroundSpikeSource > | |
| CBackendContainerTrait< BlockPostPulse > | |
| CBackendContainerTrait< CADCChannelConfig > | |
| CBackendContainerTrait< CADCConfig > | |
| CBackendContainerTrait< CADCOffsetSRAMTimingConfig > | |
| CBackendContainerTrait< CADCSampleQuad > | |
| CBackendContainerTrait< CapMemBlock< Coordinates > > | |
| CBackendContainerTrait< CapMemBlockConfig< Coordinates > > | |
| CBackendContainerTrait< CapMemCell< Coordinates > > | |
| CBackendContainerTrait< ColumnCorrelationQuad > | |
| CBackendContainerTrait< ColumnCurrentQuad > | |
| CBackendContainerTrait< CommonCorrelationConfig > | |
| CBackendContainerTrait< CommonNeuronBackendConfig > | |
| CBackendContainerTrait< CommonPADIBusConfig > | |
| CBackendContainerTrait< CommonPhyConfigChip > | |
| CBackendContainerTrait< CommonPhyConfigFPGA > | |
| CBackendContainerTrait< CommonSTPConfig > | |
| CBackendContainerTrait< CommonSynramConfig > | |
| CBackendContainerTrait< CorrelationReset > | |
| CBackendContainerTrait< CrossbarInputDropCounter > | |
| CBackendContainerTrait< CrossbarNode > | |
| CBackendContainerTrait< CrossbarOutputConfig > | |
| CBackendContainerTrait< CrossbarOutputEventCounter > | |
| CBackendContainerTrait< CurrentDAC > | |
| CBackendContainerTrait< DAC6573ChannelConfig > | |
| CBackendContainerTrait< DACChannel > | |
| CBackendContainerTrait< DACControl > | |
| CBackendContainerTrait< EventRecordingConfig > | |
| CBackendContainerTrait< ExternalPPUMemoryByte > | |
| CBackendContainerTrait< ExternalPPUMemoryQuad > | |
| CBackendContainerTrait< FPGADeviceDNA > | |
| CBackendContainerTrait< HicannARQStatus > | |
| CBackendContainerTrait< INA219Config > | |
| CBackendContainerTrait< INA219Status > | |
| CBackendContainerTrait< InstructionTimeoutConfig > | |
| CBackendContainerTrait< JTAGClockScaler > | |
| CBackendContainerTrait< JTAGIdCode > | |
| CBackendContainerTrait< MADCConfig > | |
| CBackendContainerTrait< MADCControl > | |
| CBackendContainerTrait< NeuronBackendConfig< Coordinates > > | |
| CBackendContainerTrait< NeuronBackendSRAMTimingConfig > | |
| CBackendContainerTrait< NeuronReset > | |
| CBackendContainerTrait< NeuronSRAMTimingConfig > | |
| CBackendContainerTrait< NullPayloadReadable > | |
| CBackendContainerTrait< PADIEvent > | |
| CBackendContainerTrait< PadMultiplexerConfig > | |
| CBackendContainerTrait< PerfTest > | |
| CBackendContainerTrait< PerfTestStatus > | |
| CBackendContainerTrait< PhyConfigChip > | |
| CBackendContainerTrait< PhyConfigFPGA > | |
| CBackendContainerTrait< PhyStatus > | |
| CBackendContainerTrait< PLLSelfTest > | |
| CBackendContainerTrait< PLLSelfTestStatus > | |
| CBackendContainerTrait< PollingOmnibusBlock > | |
| CBackendContainerTrait< PollingOmnibusBlockConfig > | |
| CBackendContainerTrait< PPUControlRegister > | |
| CBackendContainerTrait< PPUMemory > | |
| CBackendContainerTrait< PPUMemoryBlock > | |
| CBackendContainerTrait< PPUMemoryWord > | |
| CBackendContainerTrait< PPUStatusRegister > | |
| CBackendContainerTrait< ReadoutSourceSelection > | |
| CBackendContainerTrait< ResetChip > | |
| CBackendContainerTrait< ResetJTAGTap > | |
| CBackendContainerTrait< ShiftRegister > | |
| CBackendContainerTrait< SpikeCounterRead > | |
| CBackendContainerTrait< SpikeCounterReset > | |
| CBackendContainerTrait< SpikePack1ToChip > | |
| CBackendContainerTrait< SpikePack2ToChip > | |
| CBackendContainerTrait< SpikePack3ToChip > | |
| CBackendContainerTrait< SynapseBiasSelection > | |
| CBackendContainerTrait< SynapseCorrelationCalibQuad > | |
| CBackendContainerTrait< SynapseDriverConfig > | |
| CBackendContainerTrait< SynapseDriverSRAMTimingConfig > | |
| CBackendContainerTrait< SynapseLabelQuad > | |
| CBackendContainerTrait< SynapseQuad > | |
| CBackendContainerTrait< SynapseWeightQuad > | |
| CBackendContainerTrait< SystimeSync > | |
| CBackendContainerTrait< SystimeSyncBase > | |
| CBackendContainerTrait< TCA9554Config > | |
| CBackendContainerTrait< TCA9554Inputs > | |
| CBackendContainerTrait< Timer > | |
| CBackendContainerTrait< v2::NeuronConfig > | |
| CBackendContainerTrait< v2::NeuronResetQuad > | |
| CBackendContainerTrait< v2::PLLClockOutputBlock > | |
| CBackendContainerTrait< v2::ReferenceGeneratorConfig > | |
| CBackendContainerTrait< v3::NeuronConfig > | |
| CBackendContainerTrait< v3::NeuronResetQuad > | |
| CBackendContainerTrait< v3::PLLClockOutputBlock > | |
| CBackendContainerTrait< v3::ReferenceGeneratorConfig > | |
| CBackendContainerTrait< VectorGeneratorControl > | |
| CBackendContainerTrait< VectorGeneratorFIFOWord > | |
| CBackendContainerTrait< VectorGeneratorLUTEntry > | |
| CBackendContainerTrait< VectorGeneratorNotificationAddress > | |
| CBackendContainerTrait< VectorGeneratorTrigger > | |
| Cgen_is_read_and_writeable_lookup_table | Generate lookup table from backend to readable and writable property |
| Cgen_is_read_and_writeable_lookup_table< hate::type_list< Ts... > > | |
| CIsReadable | |
| CIsReadable< T, std::enable_if_t< hate::is_in_type_list< T, NonLeafNodeReadableContainerList >::value > > | |
| CIsReadable< T, typename boost::enable_if_has_type< decltype(T::config_size_in_words)>::type > | |
| CIsReadable< T, typename boost::enable_if_has_type< decltype(T::read_config_size_in_words)>::type > | |
| CIsWriteable | |
| CIsWriteable< T, std::enable_if_t< hate::is_in_type_list< T, NonLeafNodeWriteableContainerList >::value > > | |
| CIsWriteable< T, typename boost::enable_if_has_type< decltype(T::config_size_in_words)>::type > | |
| CIsWriteable< T, typename boost::enable_if_has_type< decltype(T::write_config_size_in_words)>::type > | |
| CIsWriteReadable | |
| CMADCSampleFromChipChecker | |
| ►CPhyConfigBase | Common base class for PhyConfig of the FPGA- and chip-side PHYs |
| CDebugOutputs | |
| CManualDelay | |
| CVBias | |
| CSpikeFromChipChecker | |
| ►CSRAMTimingConfig | Configuration of full-custom SRAM timing |
| CAddressSetupTime | Wait time for address value propagation after enable signal pull |
| CEnableWidth | Duration of enable signal pull |
| CReadDelay | Wait time after enable signal pull for cells to drive their value until read |
| CVisitPreorderImpl | Implementation detail of the visit_preorder() free function (q.v.) |
| CVisitPreorderImpl< CapMemBlock< Coordinates > > | |
| CVisitPreorderImpl< PPUMemory > | |
| CVisitPreorderImpl< PPUMemoryBlock > | |
| ►Nv2 | |
| Ndetail | |
| ►CNeuronConfig | |
| CMembraneCapacitorSize | Size of membrane capacitor |
| CNeuronResetQuad | Container to trigger reset of a quad of neurons at once |
| ►CPLLClockOutputBlock | Container for configuration of the clock outputs of the PLL |
| CClockOutput | |
| ►Nv3 | |
| Ndetail | |
| ►CNeuronConfig | |
| CMembraneCapacitorSize | Size of membrane capacitor |
| CNeuronResetQuad | Container to trigger reset of a quad of neurons at once |
| ►CPLLClockOutputBlock | Container for configuration of the clock outputs of the PLL |
| CClockOutput | |
| ►CAD5252ChannelConfig | |
| CWiperSetting | |
| ►CAD5252ChannelConfigPersistent | |
| CWiperSetting | |
| CAddPickle | Add pickle support to list of classes |
| CAddPickle< hate::type_list< Ts... > > | |
| ►CADPLL | Container for configuration of an ADPLL (All-Digital Phased-Locked-Loop) clock generator |
| CCoreDivM0 | Divider to set the output frequency f_clk_core0 (Together with PreDivP1) |
| CCoreDivM1 | Divider to set the output frequency f_clk_core1 (Together with PreDivP1) |
| CDcoPowerSwitch | Number of activated PMOS header power switches during DCO operation |
| CFilterShift | Loop filter gain boost by 2^n during lock-in, leads to lock time reduction |
| CLoopDivN | Divider to set the frequency of the DCO f_dco (Together with PreDivP0) |
| CLoopFilterInt | Integral part of the PID controller for the DCO |
| CLoopFilterProp | Proportional part of the PID controller for the DCO |
| CPreDivP0 | Divider to set the frequency of the DCO f_dco (Together with LoopDivN) |
| CPreDivP1 | Divider for f_clk_core0 and f_clk_core1 |
| CPreDivP2 | Divider to set the output frequency f_clk_dco |
| CTune | Tune value of the DCO |
| ►CBackgroundSpikeSource | Background spike source on chip |
| CMask | NeuronLabel bit randomization mask |
| CPeriod | Inter-spike interval for regular and inter-bin interval for Poisson spike generation |
| CRate | Rate of spike output in the Poisson spike generation mode, without effect in regular mode |
| CSeed | Random seed for random number generation |
| CBarrier | |
| CBlockPostPulse | Container to send post pulses to one half of the neurons (left/right) |
| ►CCADCChannelConfig | CADC container with channel-local digital offset config |
| COffset | Offset value to add to measurement |
| ►CCADCConfig | CADC container with global digital config for a vertical half |
| CDeadTime | Dead time in cycles after linear ramp increase to wait for signal propagation to every channel to prevent cutting off leaf channel ramps too early |
| CResetWait | Wait time in cycles after ramp drop to compensate for analog low-pass filtering of ramp signal and preventing the drop of the last ramp to cause interference in the next linear ramp increase |
| CCADCOffsetSRAMTimingConfig | |
| ►CCADCSampleQuad | CADC container of four CADC samples |
| CValue | CADC measurement value (offset-corrected, see CADCChannelConfig) |
| CCapMemBlock | |
| ►CCapMemBlockConfig | |
| CBoostA | |
| CBoostB | |
| CBoostFactor | |
| CCurrentCellRes | |
| CLevelShifterBias | |
| COutAmpBias | |
| CPauseCounter | |
| CPrescalePause | |
| CPrescaleRamp | |
| CPulseA | |
| CPulseB | |
| CSourceFollowerBias | |
| CSubCounter | |
| CVGlobalBias | |
| ►CCapMemCell | |
| CDisableRefresh | |
| CValue | |
| ►CColumnCorrelationQuad | |
| CColumnCorrelationSwitch | |
| ►CColumnCurrentQuad | |
| CColumnCurrentSwitch | |
| ►CCommonCorrelationConfig | Correlation reset and readout timing configuration container |
| CResetDuration | Duration of correlation reset for synapses (+3 ppu clock cycles) |
| CResetFallTime | Wait time in PPU clock cycles after disabling the correlation column reset enable |
| CSenseDelay | Wait time in PPU clock cycles between connecting the outputs of a synapse to the CADC inputs and starting the CADC read |
| ►CCommonNeuronBackendConfig | Read/write access to common neuron parameters |
| CClockScale | The ClockScale determines the range of the clock and at its precision It's an exponential power-of-two clock scaling factor: For a given reference clock of f_clk = 250MHz, the resulting frequency is f_clk / (2 ^ (clock_scale + 1)) |
| CWaitFireNeuron | Duration of pulse triggering the artificial neuron spikes |
| CWaitGlobalPostPulse | Duration of the pulse triggering global post pulses for all neurons connected to that backend block |
| CWaitSpikeCounterRead | Wait time for letting the neuron backend circuits drive the counter content to the controller logic |
| CWaitSpikeCounterReset | Duration of the pulse triggering spike counter resets |
| ►CCommonPADIBusConfig | Configuration for a PADI bus block |
| CDacenPulseExtension | |
| CCommonPhyConfigChip | Container for configuration of enable values for the chip-side PHYs |
| CCommonPhyConfigFPGA | Container for configuration of enable values for the FPGA-side PHYs |
| ►CCommonSTPConfig | Common STP configuration shared by synapse drivers per vertical half |
| CRecoveryClockSpeed | |
| ►CCommonSynramConfig | |
| CPCConf | Precharge configuration |
| CWaitCtrClear | |
| CWConf | Wordline activation delay |
| CCorrelationReset | Container to trigger reset of correlation measurements on a synapse quad |
| ►CCrossbarInputDropCounter | Crossbar input drop counter accumulating drops at all outputs for which the drop counter accumulation is enabled in the corresponding CrossbarNode |
| CValue | |
| CCrossbarNode | Node of the crossbar routing events from a CrossbarInputOnDLS to a CrossbarOutputOnDLS |
| CCrossbarOutputConfig | |
| ►CCrossbarOutputEventCounter | Crossbar output event counter counting events routed to an output |
| CValue | |
| ►CCurrentDAC | Configuration of the current DAC of the readout chain |
| CCurrent | Value of current DAC |
| ►CDAC6573ChannelConfig | |
| CValue | |
| ►CDACChannel | Container for individual configuration of the value of a DAC channel of the xBoard DACs |
| CValue | |
| CDACControl | Container for enabling DAC channels of a xBoard DAC |
| CDifferentialWriteTrait | Trait signalling derived-from container type support differential write operation |
| CEventRecordingConfig | Container for the event (spikes, MADC samples) recording configuration register |
| ►CExternalPPUMemoryByte | |
| CValue | |
| CExternalPPUMemoryQuad | |
| CFPGADeviceDNA | Container for reading out the unique identifier of the FPGA |
| CHasLocalData | |
| CHasLocalData< T, typename boost::enable_if_has_type< typename T::has_local_data >::type > | |
| CHasLocalData< T, typename boost::enable_if_has_type< typename T::is_leaf_node >::type > | |
| ►CHicannARQStatus | |
| CReadCount | Number of words submitted to the ARQ from the Chip |
| CRxCount | Number of words sent from the ARQ from the Chip to the FPGA |
| CTxCount | Number of words sent from the ARQ from the FPGA to the Chip |
| CWriteCount | Number of words submitted to the ARQ from the FPGA |
| CHighspeedLinkNotification | Highspeed-Link notification from chip |
| CINA219Config | |
| ►CINA219Status | |
| CBusVoltage | Bus voltage with linear conversion and LSB = 4mV |
| CShuntVoltage | Shunt voltage with linear conversion and LSB = 10uV |
| CUncalibratedPower | Uncalibrated power [W] |
| CInstructionTimeoutConfig | Container for the configuration of the playback instruction timeout duration |
| ►CJTAGClockScaler | Container writing JTAG clock-scaler value |
| CValue | Clock-scaler value type |
| ►CJTAGIdCode | Container for reading the JTAG IDCODE |
| CManufacturerId | JEDEC Manufacturer ID code, Heidelberg University has '0x057' |
| CPartNumber | Device identification number |
| CVersion | Hardware revision number, starting from 0 |
| ►CMADCConfig | Configuration container for MADC and related circuitry |
| CActiveMuxInputSelectLength | |
| CCalibrationWaitValue | |
| CConversionCyclesOffset | |
| CMADCClockScaleValue | |
| CNumberOfSamples | |
| CPowerupWaitValue | |
| CPreampGainCapacitorSize | |
| CSampleDurationAdjust | |
| CSamplingWindowTiming | |
| CSARResetLength | |
| CSARResetWait | |
| CMADCControl | Container for MADC control state machine |
| ►CMADCSampleFromChip | MADCSample from chip |
| CValue | Sample value |
| CNeuronBackendAddressOut | Address of the spikes sent out by a neuron |
| ►CNeuronBackendConfig | Read/write access to the NeuronBackend container |
| CInputClock | There are two independent but equivalent clocks available |
| CRefractoryTime | The refractory time can be configured to be used for different applications (short and long) Refactory Periods usually range from 0 to 5 ms |
| CResetHoldoff | ResetHoldoff period: Adjusts the time delta between the reset and the refractory period |
| CNeuronBackendSRAMTimingConfig | |
| CNeuronReset | Container to trigger reset of a single neuron |
| CNeuronSRAMTimingConfig | |
| CNullPayloadReadable | |
| ►CPADIEvent | A container for the PADI event trigger register |
| CHagenActivation | Activation payload in Hagen-mode |
| CHagenAddress | Address in Hagen-mode |
| CRowSelectAddress | |
| CPadMultiplexerConfig | A configuration container for the top-level readout mux, selecting the connections between an analog readout pad and different components on the chip |
| CPerfTest | Container for enabling highspeed perf test |
| ►CPerfTestStatus | Container for perf test result readout |
| CErrorWord | First non-consecutive payload |
| CInOrder | Number of words received in order |
| CReceived | Number of words received |
| CSent | Number of words sent successfully |
| CPhyConfigChip | Container for individual configuration of chip-side PHYs |
| CPhyConfigFPGA | Container for individual configuration of FPGA-side PHYs |
| ►CPhyStatus | |
| CCRCErrorCount | Number of CRC errors since last reset |
| COnlineTime | Online time in cycles since last reset |
| CRxCount | Number of rx words from Chip since last reset |
| CRxDroppedCount | Number of dropped rx words |
| CTxCount | Number of tx words to Chip since last reset |
| ►CPLLSelfTest | Container for configuration and triggering of the PLL internal self test |
| CCheckRange | Acceptance range for the internal counter compared to the expected counter |
| CCheckValue | Expected counter value within the 2^(p + 2) reference cycles |
| CPreScalerP | Selects counting window of the self test |
| ►CPLLSelfTestStatus | Container of PLL self-test status data |
| CCounterValue | Measured counter value in previous self-test execution |
| CPollingOmnibusBlock | Container for polling block operation on a Omnibus address |
| CPollingOmnibusBlockConfig | |
| CPPUControlRegister | |
| CPPUMemory | |
| CPPUMemoryBlock | |
| ►CPPUMemoryWord | |
| CValue | |
| CPPUStatusRegister | |
| ►CReadoutSourceSelection | Configuration container for the two mux and buffer blocks for voltage readout |
| CSourceMultiplexer | |
| CResetChip | Container for setting the reset pin of the chip |
| CResetJTAGTap | Container for resetting JTAG state-machine |
| CShiftRegister | Container for configuration of the 24-bit wide shift register controlling six VDD switches, the selection of the ADC source, ADC power down and reset pins, six LEDs, routing two DAC channels to a differential debug line and the CapMem reference current connection |
| ►CSpikeCounterRead | Container to read the spike counter of a single neuron |
| CCount | Count of rate counter |
| CSpikeCounterReset | Container to reset the spike counter of a single neuron |
| CSpikeFromChip | Spike from chip |
| ►CSpikeLabel | |
| CPADILabel | Label type processed by PADI-bus, bits 0-10 |
| CSpikePack1ToChip | |
| CSpikePack2ToChip | |
| CSpikePack3ToChip | |
| CSynapseBiasSelection | |
| ►CSynapseCorrelationCalibQuad | |
| CAmpCalib | |
| CTimeCalib | |
| ►CSynapseDriverConfig | |
| CHagenDACOffset | |
| COffset | |
| CRecovery | |
| CRowAddressCompareMask | |
| CTargetVoltages | |
| CUtilization | |
| CSynapseDriverSRAMTimingConfig | |
| CSynapseLabelQuad | |
| CSynapseLabelValue | Value type of a single synapse label configuration |
| CSynapseQuad | |
| ►CSynapseWeightQuad | |
| CValue | |
| CSystimeSync | Container for syncronization of chip and FPGA systime |
| ►CSystimeSyncBase | Container for configuring the initial counter value of the systime counter in the chip and in the FPGA after the next systime syncronization operation |
| CValue | |
| CTCA9554Config | |
| CTCA9554Inputs | |
| ►CTimer | Container for resetting the FPGA playback timer |
| CValue | |
| ►CVectorGeneratorControl | |
| CEventPack | Event packing to use |
| CResendCount | Number of times to resend same input |
| CSourceCount | Number of sources to use |
| CWait | Wait value to use |
| CVectorGeneratorFIFOWord | Container for writing a word of (maximally) four activation values into the FIFO in front of the vector generator |
| ►CVectorGeneratorLUTEntry | Container for an entry in the lookup-table for generation of spike events from activation values |
| CValue | Entry value describing the bits [5, 15] of the sent spike label |
| CVectorGeneratorNotificationAddress | |
| CVectorGeneratorTrigger | |
| ▼Nlola | |
| ►Nvx | |
| Nv2 | |
| Nv3 | |
1.9.1