pll.h File Reference
#include <array>#include <iosfwd>#include "halco/common/geometry.h"#include "halco/common/typed_array.h"#include "halco/hicann-dls/vx/pll.h"#include "haldls/cerealization.h"#include "haldls/vx/constants.h"#include "haldls/vx/genpybind.h"#include "haldls/vx/traits.h"#include "hate/visibility.h"
Include dependency graph for pll.h: This graph shows which files directly or indirectly include this file:Go to the source code of this file.
Classes | |
| class | haldls::vx::ADPLL |
| Container for configuration of an ADPLL (All-Digital Phased-Locked-Loop) clock generator. More... | |
| struct | haldls::vx::detail::BackendContainerTrait< ADPLL > |
| The JTAGPLLRegister backend only provides write functionality, but is safe with respect to changing the ADPLL config. More... | |
| struct | haldls::vx::detail::BackendContainerTrait< PLLSelfTest > |
| struct | haldls::vx::detail::BackendContainerTrait< PLLSelfTestStatus > |
| struct | haldls::vx::PLLSelfTest::CheckRange |
| Acceptance range for the internal counter compared to the expected counter. More... | |
| struct | haldls::vx::PLLSelfTest::CheckValue |
| Expected counter value within the 2^(p + 2) reference cycles. More... | |
| struct | haldls::vx::ADPLL::CoreDivM0 |
| Divider to set the output frequency f_clk_core0 (Together with PreDivP1). More... | |
| struct | haldls::vx::ADPLL::CoreDivM1 |
| Divider to set the output frequency f_clk_core1 (Together with PreDivP1). More... | |
| struct | haldls::vx::PLLSelfTestStatus::CounterValue |
| Measured counter value in previous self-test execution. More... | |
| struct | haldls::vx::ADPLL::DcoPowerSwitch |
| Number of activated PMOS header power switches during DCO operation. More... | |
| struct | haldls::vx::ADPLL::FilterShift |
| Loop filter gain boost by 2^n during lock-in, leads to lock time reduction. More... | |
| struct | haldls::vx::ADPLL::LoopDivN |
| Divider to set the frequency of the DCO f_dco (Together with PreDivP0). More... | |
| struct | haldls::vx::ADPLL::LoopFilterInt |
| Integral part of the PID controller for the DCO. More... | |
| struct | haldls::vx::ADPLL::LoopFilterProp |
| Proportional part of the PID controller for the DCO. More... | |
| class | haldls::vx::PLLSelfTest |
| Container for configuration and triggering of the PLL internal self test. More... | |
| class | haldls::vx::PLLSelfTestStatus |
| Container of PLL self-test status data. More... | |
| struct | haldls::vx::ADPLL::PreDivP0 |
| Divider to set the frequency of the DCO f_dco (Together with LoopDivN). More... | |
| struct | haldls::vx::ADPLL::PreDivP1 |
| Divider for f_clk_core0 and f_clk_core1. More... | |
| struct | haldls::vx::ADPLL::PreDivP2 |
| Divider to set the output frequency f_clk_dco. More... | |
| struct | haldls::vx::PLLSelfTest::PreScalerP |
| Selects counting window of the self test. More... | |
| struct | haldls::vx::ADPLL::Tune |
| Tune value of the DCO. More... | |
Namespaces | |
| halco | |
| halco::hicann_dls | |
| halco::hicann_dls::vx | |
| haldls | |
| haldls::vx | |
| haldls::vx::detail | |
Functions | |
| std::ostream & | haldls::vx::operator<< (std::ostream &, ADPLL::Output const &) SYMBOL_VISIBLE |
