28 GENPYBIND(getter_for(enable_output))
29 bool get_enable_output() const SYMBOL_VISIBLE;
35 GENPYBIND(setter_for(enable_output))
36 void set_enable_output(
bool value) SYMBOL_VISIBLE;
43 GENPYBIND(getter_for(enable_bypass))
44 bool get_enable_bypass() const SYMBOL_VISIBLE;
51 GENPYBIND(setter_for(enable_bypass))
52 void set_enable_bypass(
bool value) SYMBOL_VISIBLE;
58 GENPYBIND(getter_for(select_adpll))
59 halco::hicann_dls::vx::ADPLLOnDLS get_select_adpll() const SYMBOL_VISIBLE;
65 GENPYBIND(setter_for(select_adpll))
66 void set_select_adpll(
halco::hicann_dls::vx::ADPLLOnDLS const& coord) SYMBOL_VISIBLE;
72 GENPYBIND(getter_for(select_adpll_output))
73 ADPLL::Output get_select_adpll_output() const SYMBOL_VISIBLE;
79 GENPYBIND(setter_for(select_adpll_output))
80 void set_select_adpll_output(
ADPLL::Output const value) SYMBOL_VISIBLE;
82 bool operator==(
ClockOutput const& other) const SYMBOL_VISIBLE;
83 bool operator!=(
ClockOutput const& other) const SYMBOL_VISIBLE;
85 GENPYBIND(stringstream)
86 friend std::ostream& operator<<(std::ostream& os,
ClockOutput const& config) SYMBOL_VISIBLE;
90 template <typename Archive>
91 void serialize(Archive& ar, std::uint32_t const version) SYMBOL_VISIBLE;
95 halco::hicann_dls::vx::ADPLLOnDLS m_adpll;
96 ADPLL::Output m_adpll_output;
110 halco::hicann_dls::vx::PLLClockOutputOnDLS const& coord) const SYMBOL_VISIBLE;
117 void set_clock_output(
118 halco::hicann_dls::vx::PLLClockOutputOnDLS const& coord,
124 GENPYBIND(stringstream)
128 static
size_t constexpr config_size_in_words GENPYBIND(hidden) = 1;
129 template <typename AddressT>
130 static std::array<AddressT, config_size_in_words> addresses(
coordinate_type const& coord)
131 SYMBOL_VISIBLE GENPYBIND(hidden);
132 template <typename WordT>
133 std::array<WordT, config_size_in_words> encode() const SYMBOL_VISIBLE GENPYBIND(hidden);
134 template <typename WordT>
135 void decode(std::array<WordT, config_size_in_words> const& data) SYMBOL_VISIBLE
140 template <typename Archive>
141 void serialize(Archive& ar, std::uint32_t const version) SYMBOL_VISIBLE;
148 namespace
haldls::vx::detail {
153 v2::PLLClockOutputBlock,
154 fisch::vx::word_access_type::JTAGPLLRegister,
155 fisch::vx::word_access_type::OmnibusChipOverJTAG>
#define EXTERN_INSTANTIATE_CEREAL_SERIALIZE(CLASS_NAME)
Container for configuration of an ADPLL (All-Digital Phased-Locked-Loop) clock generator.
Container for configuration and triggering of the PLL internal self test.
Container of PLL self-test status data.
ClockOutput() SYMBOL_VISIBLE
Default construct PLL clock output.
Container for configuration of the clock outputs of the PLL.
halco::hicann_dls::vx::PLLClockOutputBlockOnDLS coordinate_type
std::true_type is_leaf_node
#define GENPYBIND_TAG_HALDLS_VX_V2
haldls::vx::PLLSelfTestStatus PLLSelfTestStatus
haldls::vx::PLLSelfTest PLLSelfTest
Backend container trait base.